Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. Memory devices that do not lose the data content of their memory cells when power is removed are generally referred to as non-volatile memories. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. A typical floating gate memory cell is fabricated in an integrated circuit substrate and includes a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A conductive floating gate, typically made of doped polysilicon, or non-conductive charge trapping layer (a floating node), such as nitride (as would be utilized in a silicon-oxide-nitride-oxide-silicon or SONOS gate-insulator stack), is disposed over the channel region and is electrically isolated from the other cell elements by a dielectric material, typically an oxide. For example, a tunnel oxide that is formed between the floating gate/node and the channel region. A control gate is located over the floating gate/node and is typically made of doped polysilicon or metal. The control gate is electrically separated from the floating gate/node by another dielectric layer. Thus, the floating gate or charge trapping layer/floating node is “floating” in dielectric so that it is insulated from both the channel and the control gate. Charge is transported to or removed from the floating gate or trapping layer by specialized programming and erase operations, respectively, altering the threshold voltage of the device.
Yet another type of non-volatile memory is a Flash memory. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate or charge trapping layer embedded in a field effect transistor (FET) transistor. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed by tunneling charges to its individual floating gate/node. Unlike programming operations, however, erase operations in Flash memories typically erase the memory cells in bulk erase operations, wherein all floating gate/node memory cells in a selected erase block are erased in a single operation. It is noted that in recent Flash memory devices multiple bits have been stored in a single cell by utilizing multiple threshold levels or a non-conductive charge trapping layer with the storing of data trapped in a charge near each of the sources/drains of the memory cell FET.
An EEPROM or Flash NAND array architecture arranges its array of non-volatile memory cells in a matrix of rows and columns, as a conventional NOR array does, so that the gates of each non-volatile memory cell of the array are coupled by rows to word lines (WLs). However, unlike NOR, each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. This allows a NAND array architecture to have a higher memory cell density than a comparable NOR array, but with the cost of a generally slower access rate and programming complexity. It is noted that other non-volatile memory array architectures exist, including, but not limited to AND arrays, OR arrays, and virtual ground arrays.
A problem in modern NAND architecture Flash memory devices is that, as device sizes and features are further reduced with improved processing, the separation between adjacent word lines in the array is reduced (also known as an increased word line or memory cell “array pitch”). This reduced word line separation can increase capacitive coupling between adjacent word lines, particularly when they have elevated voltages applied to them and/or high voltage differentials exist between adjacent word lines, such as during programming operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods of programming and accessing NAND architecture Flash memory arrays.